Today there was a webinar (web + seminar) by Mentor Graphics on “Hardware Designs Reuse Using C++ and High Level Synthesis.” The lecture in bullet points:
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ANSI C++ synthesis into RTL is supported;
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a 10–20x increase in engineers’ productivity, as well as reduced verification time;
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synthesis quality equivalent to manual work;
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various parameterizable data types are available that synthesize well into hardware;
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object-oriented device architecture: for example, you can make devices with one interface but different implementations;
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you can view the results of micro-operation execution scheduling on a Gantt chart: timing delays, distribution by clock cycles.
Overall, I heard nothing new since spring. At the end there was a chance to ask the lecturer questions with a finger on the keyboard, and listen to the answer with an ear from the speaker. I asked the following questions and got specific answers.
Question: how are things with SystemC support? Answer*: our users mostly use pure C++, because they are programmers and don’t know SystemC at all.
Question: how does joint software-hardware synthesis happen? Answer: it doesn’t. At the moment this is just a tool for C++ to RTL synthesis, and that’s all.
Question: is it necessary to use any C++ extensions or directives? Answer: no, it isn’t. Our C++ models can easily be fed to any compiler and you will get the exact same simulation results. Directives can be used in cases when it is necessary to specify parallelism in a loop, etc.
here and below, a loose retelling*
There is an opportunity to watch more detailed demonstrations on the Mentor Graphics site.
We continue working on our translator. Among the nearest tasks: function inlining, expression optimization.